Views: 276 Author: James Wu Publish Time: 2020-09-12 Origin: Site
As one of the most commonly used peripheral interfaces for embedded smart devices, SPI is the abbreviation of “Serial Peripheral Interface”, which is a standard four-wire synchronous two-way serial bus. SPI was first defined by Motorola on its MC68HCXX series processors. SPI interface is mainly used between EEPROM, FLASH, real-time clock, AD converter, digital signal processor and digital signal decoder.
The SPI bus system is a synchronous serial peripheral interface, which enables the MCU to communicate with various peripheral devices in a serial manner to exchange information. Peripheral settings FLASHRAM, network controller, LCD display driver, A/D converter and MCU, etc. It is a high-speed, full-duplex, and synchronous communication bus, and only occupies four wires on the pins of the chip, saving the pins of the chip, and at the same time saving space and convenience for the PCB layout. Because of this simple and easy-to-use feature, more and more chips now integrate this communication protocol.
The SPI bus system can directly interface with a variety of standard peripheral devices produced by various manufacturers. The interface generally uses 4 wires, so it is often called a four-wire serial bus, working in a master/slave mode, and the data transmission process is initialized by the master device.
The four signal lines are as follows:
1. SCLK: Serial Clock line
2. MISO: Master Input/Slave Output data line
3. MOSI: Master Output/Slave Input data line
4. SS: Chip Select line, output by the master, selected by the slave, low level active;
Note: Some SPI interface chips also have an interrupt signal line (INT), and some SPI interface chips do not have a MOSI line.
The SPI bus can realize the interconnection of multiple SPI devices with simple operation and high data transmission rate. Full-duplex communication can be realized between master and slave devices. When there are multiple slave devices, a slave device selection line can be added. On the SPI bus, multiple slaves can appear at a certain time, but there can only be one master, and the master determines the slave to communicate through chip selection. This requires the MISO port of the slave machine to have a tri-state feature, which makes the port line appear as high impedance when the device is not strobed
Note: SPI only supports a single SPI Master (SPI device that provides SPI serial clock is SPI Master, and other devices are SPI Slave), and each slave needs an SS chip select line.
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